With the rapid increase of a single processor processing ability, to construct a high-available, high-density and ultra-scalable supercomputer faces the embarrassing bottleneck of the communication subsystem design, whose developments and innovations dramatically lags behind the computation power. To better manage the consistent balance between the communication and computation in a large-scale supercomputer while to preserve the programmability and application portability, more and more advanced interconnect topologies are put into practice such as IBM BlueGene and Cray RedStorm employing 3-D torus and Columbia QCDOC employing truncated 6-D torus. Those novel multi-dimensional mesh-based architectures with the internally developed design of the advanced interconnect intellectual properties allow systems to comprise higher processor counts and to achieve better overall performance on applications compared to the conventional systems that rely on the commodity interconnect fabrics including the external fat-tree Infiniband or Myrinet federated switch. Additionally, as observed on systems with Myrinet and Infiniband interconnects, intermittent errors on a single link may have a serious impact on the performance of the massively parallel applications by slowing down the communication due to the time required for connection recovery and data retransmission. Alternately, mesh-based network designs overcome this issue by implementing a large portion of data links as traces on the system backplanes and by aggregating several alternative connections into a single bundle attached to a single socket, thus reducing impact caused by the number of possible mechanical faults by an order of magnitude.
Further, due to the absence of the more centralized external federated switch formed by a large number of individual switches, a mesh-based supercomputer is more flexible to be expanded without losing scalability. However, a similar-scale cluster design with several thousand nodes necessarily has to contain much more external cables connecting the nodes to tens of switches that must be located tens of meters or more away from each other. Such scenario is also a serious maintenance disaster, in addition to much higher operating expenses. The fault tolerance ability of a cluster system important for achieving the sustained and reliable computing resources for large-scale realistic applications is always guaranteed at the sacrifice of more redundant switches available, thus increasing the size of external federated switches again. However, the novel mesh-based supercomputers, such as IBM BlueGene, use smart adaptive routing strategies to isolate the fault area while routing messages with existing alternative data links around fault nodes flexibly without demanding much more hardware compensation to retain the communication balance by dynamic fault-tolerant routing algorithms.
The trends of the high-performance computing (HPC) industry strongly indicate the value of the present invention in providing an ultra-scalable supercomputer based on MPU architecture. The MPU architecture is a novel multi-dimensional network topology enabling an ultra-scalable and highly coupled interconnection while, by adding Axon nodes, providing facilitating long-range and collective communications and also for connections to external networks such as the management and external file networks. Preferably, considering both high compatibility with different processor platforms and flexible adaptability with varied application acceleration units while better and stably implementing our own IP cores, we choose the reconfigurable chip as the implementation platform of the switching logic for a processing node or an Axon node.